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19-1155; Rev 2; 11/98
KIT ATION EVALU ABLE AVAIL
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO
________________________________Features
o Single-Supply Operation: +2.7V to +3.6V (MAX1240) +2.7V to +5.25V (MAX1241) o o o o 12-Bit Resolution Internal 2.5V Reference (MAX1240) Small Footprint: 8-Pin DIP/SO Packages Low Power: 3.7W (73ksps, MAX1240) 3mW (73ksps, MAX1241) 66W (1ksps, MAX1241) 5W (power-down mode)
__________________General Description
The MAX1240/MAX1241 are low-power, 12-bit analogto-digital converters (ADCs) available in 8-pin packages. The MAX1240 operates with a single +2.7V to +3.6V supply, and the MAX1241 operates with a single +2.7V to +5.25V supply. Both devices feature a 7.5s successive-approximation ADC, a fast track/hold (1.5s), an on-chip clock, and a high-speed, 3-wire serial interface. Power consumption is only 37mW (VDD = 3V) at the 73ksps maximum sampling speed. A 2A shutdown mode reduces power at slower throughput rates. The MAX1240 has an internal 2.5V reference, while the MAX1241 requires an external reference. The MAX1241 accepts signals from 0V to VREF, and the reference input range includes the positive supply rail. An external clock accesses data from the 3-wire interface, which connects directly to standard microcontroller I/O ports. The interface is compatible with SPITM, QSPITM, and MICROWIRETM. Excellent AC characteristics and very low power combined with ease of use and small package size make these converters ideal for remote-sensor and dataacquisition applications, or for other circuits with demanding power consumption and space requirements. The MAX1240/MAX1241 are available in 8-pin DIP and SO packages.
MAX1240/MAX1241
o Internal Track/Hold o SPI/QSPI/MICROWIRE 3-Wire Serial Interface o Internal Clock
Ordering Information
PART MAX1240ACPA MAX1240BCPA MAX1240CCPA MAX1240ACSA MAX1240BCSA MAX1240CCSA MAX1240BC/D TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C PINPACKAGE 8 Plastic DIP 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO 8 SO Dice* INL (LSB) 1/2 1 1 1/2 1 1 1
Applications
Battery-Powered Systems Portable Data Logging Isolated Data Acquisition Process Control Instrumentation
Ordering Information continued at end of data sheet. *Dice are specified at TA = +25C, DC parameters only.
Functional Diagram
VDD 1 CS 7 8 3 CONTROL LOGIC INT CLOCK
Pin Configuration
TOP VIEW
VDD AIN 1 2 8 7 SCLK CS DOUT GND
SCLK SHDN
OUTPUT SHIFT REGISTER
6
DOUT
SHDN 3 REF 4
MAX1240 MAX1241
AIN
2
T/H 2.5V REFERENCE (MAX1240 ONLY)
12-BIT SAR
6 5
REF
4
MAX1240 MAX1241
5 GND
DIP/SO
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO MAX1240/MAX1241
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V AIN to GND................................................-0.3V to (VDD + 0.3V) REF to GND ...............................................-0.3V to (VDD + 0.3V) Digital Inputs to GND...............................................-0.3V to +6V DOUT to GND............................................-0.3V to (VDD + 0.3V) DOUT Current ..................................................................25mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 9.09mW/C above +70C) ...........727mW SO (derate 5.88mW/C above +70C)........................471mW CERDIP (derate 8.00mW/C above +70C)................640mW Operating Temperature Ranges MAX1240_C_A/MAX1241_C_A .........................0C to +70C MAX1240_E_ A/MAX1241_E_ A .....................-40C to +85C MAX1240_MJA/MAX1241_MJA ...................-55C to +125C Storage Temperature Range............................-60C to +150C Lead Temperature (soldering, 10sec) ............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX1240); VDD = +2.7V to +5.25V (MAX1241); 73ksps, fSCLK = 2.1MHz (50% duty cycle); MAX1240--4.7F capacitor at REF pin, MAX1241--external reference; VREF = 2.500V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 73ksps, fSCLK = 2.1MHz) Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Small-Signal Bandwidth Full-Power Bandwidth CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate Aperture Delay Aperture Jitter ANALOG INPUT Input Voltage Range Input Capacitance 2 0 16 VREF V pF tAPR tCONV tACQ fSCLK = 2.1MHz Figure 8 30 <50 5.5 7.5 1.5 73 s s ksps ns ps SINAD THD SFDR MAX124_A/B MAX124_C Up to the 5th harmonic MAX124_A/B MAX124_C -3dB rolloff MAX124_A/B MAX124_C 80 88 2.25 1.0 -88 70 71.5 -80 dB dB dB MHz MHz INL DNL MAX124_A MAX124_B/C No missing codes over temperature MAX124_A MAX124_B/C 0.5 0.5 0.5 0.25 12 0.5 1.0 1 3.0 4.0 4.0 Bits LSB LSB LSB LSB ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
_______________________________________________________________________________________
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX1240); VDD = +2.7V to +5.25V (MAX1241); 73ksps, fSCLK = 2.1MHz (50% duty cycle); MAX1240--4.7F capacitor at REF pin, MAX1241--external reference; VREF = 2.500V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER REF Output Voltage REF Short-Circuit Current MAX1240AC/BC REF Temperature Coefficient MAX1240AE/BE MAX1240AM/BM MAX1240C Load Regulation (Note 4) Capacitive Bypass at REF EXTERNAL REFERENCE (VREF = 2.500V) Input Voltage Range Input Current Input Resistance REF Input Current in Shutdown Capacitive Bypass at REF DIGITAL INPUTS: SCLK, CS, SHDN SCLK, CS Input High Voltage SCLK, CS Input Low Voltage SCLK, CS Input Hysteresis SCLK, CS Input Leakage SCLK, CS Input Capacitance SHDN Input High Voltage SHDN Input Low Voltage SHDN Input Current SHDN Input Mid Voltage SHDN Voltage, Floating SHDN Max Allowed Leakage, Mid Input DIGITAL OUTPUT: DOUT Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance VOL VOH IL COUT ISINK = 5mA ISINK = 16mA ISOURCE = 0.5mA CS = VDD CS = VDD (Note 5) VDD - 0.5 0.01 10 15 0.4 0.8 V V A pF VSM VFLT SHDN = float SHDN = float VIH VIL VHYST IIN CIN VSH VSL SHDN = 0V or VDD 1.1 VDD/2 100 VIN = 0V or VDD (Note 5) VDD - 0.4 0.4 4.0 VDD - 1.1 0.2 0.01 1 15 VDD 3.6V VDD > 3.6V (MAX1241) 2.0 3.0 0.8 V V V A pF V V A V V nA SHDN = 0V 0.1 18 1.00 100 25 0.01 10 VDD + 50mV 150 V A k A F 0mA to 0.2mA output load 4.7 30 30 30 30 0.35 F SYMBOL TA = +25C CONDITIONS MIN 2.480 TYP 2.500 MAX 2.520 30 50 60 80 ppm/C ppm/C UNITS V mA
MAX1240/MAX1241
INTERNAL REFERENCE (MAX1240 only)
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3
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO MAX1240/MAX1241
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX1240); VDD = +2.7V to +5.25V (MAX1241); 73ksps, fSCLK = 2.1MHz (50% duty cycle); MAX1240--4.7F capacitor at REF pin, MAX1241--external reference; VREF = 2.500V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETERS POWER REQUIREMENTS Supply Voltage VDD MAX1240 MAX1241 MAX1240A/B MAX1240C Operating mode Supply Current IDD MAX1241C Power-down, digital inputs at 0V or VDD Supply Rejection PSR (Note 5) MAX1241A/B VDD = 3.6V VDD = 3.6V VDD = 3.6V VDD = 5.25V VDD = 3.6V VDD = 5.25V VDD = 3.6V VDD = 5.25V 2.7 2.7 1.4 1.4 0.9 1.6 0.9 1.6 1.9 3.5 0.3 3.6 5.25 2.0 3.5 1.5 2.5 2.8 3.8 10 15 A mV mA V SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Figure 8)
(VDD = +2.7V to +3.6V (MAX1240); VDD = +2.7V to +5.25V (MAX1241); TA = TMIN to TMAX, unless otherwise noted.) PARAMETERS Acquisition Time SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable SCLK Clock Frequency SCLK Pulse Width High SCLK Pulse Width Low SCLK Low to CS Fall Setup Time DOUT Rise to SCLK Rise (Note 5) CS Pulse Width SYMBOL tACQ tDO tDV tTR fSCLK tCH tCL tCS0 tSTR tCS Figure 1, CLOAD = 50pF Figure 1, CLOAD = 50pF Figure 2, CLOAD = 50pF 0 200 200 50 0 240 CONDITIONS CS = VDD (Note 6) MAX124_ _C/E MAX124_ _M MIN 1.5 20 20 200 240 240 240 2.1 TYP MAX UNITS s ns ns ns MHz ns ns ns ns ns
Note 1: Tested at VDD = +2.7V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. Note 3: MAX1240--internal reference, offset nulled; MAX1241--external reference (VREF = +2.500V), offset nulled. Note 4: External load should not change during conversion for specified accuracy. Note 5: Guaranteed by design. Not subject to production testing. Note 6: Measured as [VFS(2.7V) - VFS(VDD(MAX)]. Note 7: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired.
4
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+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO MAX1240/MAX1241
+2.7V
6k DOUT 6k DGND a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL CLOAD = 50pF DOUT CLOAD = 50pF DGND
Figure 1. Load Circuits for DOUT Enable Time
+2.7V
6k DOUT 6k DGND a) VOH to High-Z b) VOLto High-Z CLOAD = 50pF DOUT CLOAD = 50pF DGND
Figure 2. Load Circuits for DOUT Disable Time
__________________________________________Typical Operating Characteristics
(VDD = 3.0V, VREF = 2.5V, fSCLK = 2.1MHz, CL = 20pF, TA = +25C, unless otherwise noted.)
OPERATING SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1241-D
SUPPLY CURRENT vs. TEMPERATURE
MAX1241-A/NEW
OFFSET ERROR vs. SUPPLY VOLTAGE
0.9 0.8 OFFSET ERROR (LSB) 0.7 0.6 0.5 0.4 0.3 0.2
MAX1241-03
2.0
OPERATING SUPPLY CURRENT (mA)
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2
RL = CODE = 101010100000 MAX1240
1.3 MAX1240
1.0
1.2 SUPPLY CURRENT (mA)
1.1
MAX1241
1.0 MAX1241 0.9 RLOAD = CODE = 10101010000 -60 -20 20 60 100 140
0.1 0 2.25 2.75 3.25 3.75 4.25 4.75 5.25 SUPPLY VOLTAGE (V)
0.8 3 4 SUPPLY VOLTAGE (V) 5 6
TEMPERATURE (C)
_______________________________________________________________________________________
5
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO MAX1240/MAX1241
____________________________Typical Operating Characteristics (continued)
(VDD = 3.0V, VREF = 2.5V, fSCLK = 2.1MHz, CL = 20pF, TA = +25C, unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1241-C/NEW
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX1241-B
OFFSET ERROR vs. TEMPERATURE
VDD = 2.7V 0.7 OFFSET ERROR (LSB) 0.6 0.5 0.4 0.3 0.2 0.1 0
MAX1241-06
4.0
SHUTDOWN SUPPLY CURRENT (A)
5.0 SHUTDOWN SUPPLY CURRENT (A) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
0.8
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2.25 2.75 3.25 3.75 4.25 4.75
5.25
-60
-20
20
60
100
140
-55
-30
-5
20
45
70
95
120 145
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
TEMPERATURE (C)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1241-07
GAIN ERROR vs. TEMPERATURE
MAX1241-08
MAX1240 INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX1241-0X
0.8 0.7 0.6 GAIN ERROR (LSB)
0.8 VDD = 2.7V 0.7 0.6 GAIN ERROR (LSB)
2.5020 2.5015 2.5010 VREF (V)
0.5 0.4 0.3 0.2 0.1 0 2.25 2.75 3.25 3.75 4.25 4.75 5.25 SUPPLY VOLTAGE (V)
0.5 0.4 0.3 0.2
2.5005 2.5000 2.4995
0.1 0 -55 -30 -5 20 45 70 95 120 145 TEMPERATURE (C) 2.4990 2.25 2.75 3.25 3.75 VDD (V) 4.25 4.75 5.25
MAX1240 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1241-0Y
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX1241-09/NEW
INTEGRAL NONLINEARITY vs. TEMPERATURE
VDD = 2.7V 1.0 0.8 INL (LSB) 0.6 0.4 MAX1240 0.2 MAX1241 0 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C)
MAX1241-10/NEW
2.501 2.500 2.499 2.498 2.497 2.496 2.495 2.494 -60 -20 20 60 100 VDD = 3.6V VDD = 2.7V VREF (V)
1.2 1.0 0.8 INL (LSB) 0.6 0.4 0.2 0 MAX1240
1.2
MAX1241 2.25 2.75 3.25 3.75 4.25 4.75 5.25
140
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
6
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+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO
____________________________Typical Operating Characteristics (continued)
(VDD = 3.0V, REF = 2.5V, fSCLK = 2.1MHz, CL = 20pF, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE
MAX1241-11A/NEW
MAX1240/MAX1241
FFT PLOT
MAX1241-TOC12A
0.6 0.4 0.2 INL (LSB) 0 -0.2 -0.4 -0.6 0 1024 2048 CODE 3072
20 0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 -140 0 fAIN = 10kHz, 2.5Vp-p fSAMPLE = 73ksps
4096
18.75 FREQUENCY (kHz)
37.50
_______________________________________________________________________Pin Description
PIN 1 2 NAME VDD AIN FUNCTION Positive Supply Voltage: 2.7V to 3.6V, (MAX1240); 2.7 to 5.25V (MAX1241) Sampling Analog Input, 0V to VREF range Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1240/MAX1241 down to 15A (max) supply current. Both the MAX1240 and MAX1241 are fully operational with either SHDN high or floating. For the MAX1240, pulling SHDN high enables the internal reference, and letting SHDN float disables the internal reference and allows for the use of an external reference. Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for MAX1240; bypass with 4.7F capacitor. External reference voltage input for MAX1241, or for MAX1240 with the internal reference disabled. Bypass REF with a minimum of 0.1F when using an external reference. Analog and Digital Ground Serial Data Output. Data changes state at SCLK's falling edge. DOUT is high impedance when CS is high. Active-Low Chip Select initiates conversions on the falling edge. When CS is high, DOUT is high impedance. Serial Clock Input. SCLK clocks data out at rates up to 2.1MHz.
3
SHDN
4 5 6 7 8
REF GND DOUT CS SCLK
_______________________________________________________________________________________
7
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO MAX1240/MAX1241
+2.7V to +3.6V* * VDD,MAX = +5.25V (MAX1241) ** 4.7F (MAX1240) 0.1F (MAX1241) 4.7F 0.1F 1 2 3 4 C** VDD SCLK 8 7 6 5 GND SERIAL INTERFACE AIN 12-BIT CAPACITIVE DAC REF TRACK INPUT CHOLD -+ 16pF CSWITCH TRACK 9k RIN HOLD AT THE SAMPLING INSTANT, THE INPUT SWITCHES FROM AIN TO GND. COMPARATOR ZERO
ANALOG INPUT 0V TO VREF SHUTDOWN INPUT REFERENCE INPUT (MAX1241 ONLY)
AIN MAX1240 CS MAX1241 SHDN REF DOUT GND
HOLD
Figure 3. Operational Diagram
Figure 4. Equivalent Input Circuit
_______________Detailed Description
Converter Operation
The MAX1240/MAX1241 use an input track/hold (T/H) and successive-approximation register (SAR) circuitry to convert an analog input signal to a digital 12-bit output. No external-hold capacitor is needed for the T/H. Figure 3 shows the MAX1240/MAX1241 in its simplest configuration. The MAX1240/MAX1241 convert input signals in the 0V to VREF range in 9s, including T/H acquisition time. The MAX1240's internal reference is trimmed to 2.5V, while the MAX1241 requires an external reference. Both devices accept voltages from 1.0V to VDD. The serial interface requires only three digital lines (SCLK, CS, and DOUT) and provides an easy interface to microprocessors (Ps). The MAX1240/MAX1241 have two modes: normal and shutdown. Pulling SHDN low shuts the device down and reduces supply current below 10A (VDD 3.6V), while pulling SHDN high or leaving it open puts the device into operational mode. Pulling CS low initiates a conversion. The conversion result is available at DOUT in unipolar serial format. The serial data stream consists of a high bit, signaling the end of conversion (EOC), followed by the data bits (MSB first).
switch opens and maintains a constant input to the ADC's SAR section. During acquisition, the analog input (AIN) charges capacitor CHOLD. Bringing CS low ends the acquisition interval. At this instant, the T/H switches the input side of CHOLD to GND. The retained charge on CHOLD represents a sample of the input, unbalancing node ZERO at the comparator's input. In hold mode, the capacitive digital-to-analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 12bit resolution. This action is equivalent to transferring a charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. At the conversion's end, the input side of C HOLD switches back to AIN, and C HOLD charges to the input signal again. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. Acquisition time is calculated by: tACQ = 9(RS + RIN) x 16pF where RIN = 9k, RS = the input signal's source impedance, and tACQ is never less than 1.5s. Source impedances below 1k do not significantly affect the ADC's AC performance.
Analog Input
Figure 4 illustrates the sampling architecture of the analog-to-digital converter's (ADC's) comparator. The fullscale input voltage is set by the voltage at REF.
Track/Hold In track mode, the analog signal is acquired and stored in the internal hold capacitor. In hold mode, the T/H
8
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+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO
Higher source impedances can be used if a 0.01F capacitor is connected to the analog input. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC's input signal bandwidth. down (see the section Using SHDN to Reduce Supply Current). The internal reference is enabled by pulling the SHDN pin high. Letting SHDN float disables the internal reference, which allows the use of an external reference, as described in the External Reference section. External Reference The MAX1240/MAX1241 operate with an external reference at the REF pin. To use the MAX1240 with an external reference, disable the internal reference by letting SHDN float. Stay within the +1.0V to VDD voltage range to achieve specified accuracy. The minimum input impedance is 18k for DC currents. During conversion, the external reference must be able to deliver up to 250A of DC load current and have an output impedance of 10 or less. The recommended minimum value for the bypass capacitor is 0.1F. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7F capacitor.
MAX1240/MAX1241
Input Bandwidth The ADCs' input tracking circuitry has a 2.25MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid aliasing of unwanted high-frequency signals into the frequency band of interest, anti-alias filtering is recommended. Analog Input Protection Internal protection diodes, which clamp the analog input to VDD and GND, allow the input to swing from GND - 0.3V to VDD + 0.3V without damage. However, for accurate conversions near full scale, the input must not exceed VDD by more than 50mV, or be lower than GND by 50mV.
If the analog input exceeds 50mV beyond the supplies, limit the input current to 2mA.
____________________Serial Interface
Initialization after Power-Up and Starting a Conversion
When power is first applied, and if SHDN is not pulled low, it takes the fully discharged 4.7F reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy. With an external reference, the internal reset time is 10s after the power supplies have stabilized. No conversions should be performed during these times. To start a conversion, pull CS low. At CS's falling edge, the T/H enters its hold mode and a conversion is initiat-
Internal Reference (MAX1240) The MAX1240 has an on-chip voltage reference trimmed to 2.5V. The internal reference output is connected to REF and also drives the internal capacitive DAC. The output can be used as a reference voltage source for other components and can source up to 400A. Bypass REF with a 4.7F capacitor. Larger capacitors increase wake-up time when exiting shut-
COMPLETE CONVERSION SEQUENCE CS tWAKE SHDN
DOUT CONVERSION 0 POWERED UP POWERED DOWN CONVERSION 1 POWERED UP
Figure 5. Shutdown Sequence
_______________________________________________________________________________________ 9
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO MAX1240/MAX1241
VDD = VREF = 3.0V RLOAD = , CLOAD = 50pF SUPPLY CURRNET (mA) 1 CODE = 010101010000
MAX1241 FIG. 06a
ed. After an internally timed conversion period, the end of conversion is signaled by DOUT pulling high. Data can then be shifted out serially with the external clock.
10
Using SHDN to Reduce Supply Current
Power consumption can be reduced significantly by shutting down the MAX1240/MAX1241 between conversions. Figure 6 shows a plot of average supply current versus conversion rate. Because the MAX1241 uses an external reference voltage (assumed to be present continuously), it "wakes up" from shutdown more quickly (in 4s) and therefore provides lower average supply currents. The wake-up time (tWAKE) is the time from when SHDN is deasserted to the time when a conversion may be initiated (Figure 5). For the MAX1240, this time depends on the time in shutdown (Figure 7) because the external 4.7F reference bypass capacitor loses charge slowly during shutdown.
0.1 MAX1240 0.01 MAX1241 0.001
0.1
1
10
100
1k
10k
100k
CONVERSION RATE (Hz)
Figure 6. Average Supply Current vs. Conversion Rate
External Clock
The actual conversion does not require the external clock. This allows the conversion result to be read back at the P's convenience at any clock rate from up to 2.1MHz. The clock duty cycle is unrestricted if each clock phase is at least 200ns. Do not run the clock while a conversion is in progress.
MAX1240/41-07a
1.0
0.8 POWER-UP DELAY (ms)
0.6
Timing and Control
Conversion-start and data-read operations are controlled by the CS and SCLK digital inputs. The timing diagrams of Figures 8 and 9 outline serial-interface operation. A CS falling edge initiates a conversion sequence: the T/H stage holds the input voltage, the ADC begins to convert, and DOUT changes from high impedance to logic low. SCLK must be kept low during the conversion. An internal register stores the data when the conversion is in progress.
0.4
0.2
0.0 0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
Figure 7. Typical Reference Power-Up Delay vs. Time in Shutdown
CS 1 SCLK DOUT EOC INTERFACE IDLE TRACK/HOLD TRACK STATE CONVERSION IN PROGRESS HOLD 7.5s (tCONV) CYCLE TIME 0s EOC CLOCK OUT SERIAL DATA TRACK 12.5 x 0.476s = 5.95s TOTAL = 13.7s 0s 0.24s (tCS) TRAILING ZEROS IDLE HOLD B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 4 8 12 16
Figure 8. Interface Timing Sequence
10 ______________________________________________________________________________________
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO MAX1240/MAX1241
CS tCS0 tCS
... ...
tCH tDO
SCLK tDV DOUT tAPR tSTR (HOLD) tCONV
tCL B2 B1 B0
tTR
... ...
INTERNAL T/H
(TRACK/ACQUIRE)
(TRACK/ACQUIRE)
Figure 9. Detailed Serial-Interface Timing
End of conversion (EOC) is signaled by DOUT going high. DOUT's rising edge can be used as a framing signal. SCLK shifts the data out of this register any time after the conversion is complete. DOUT transitions on SCLK's falling edge. The next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since there are 12 data bits and one leading high bit, at least 13 falling clock edges are needed to shift out these bits. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of CS, produce trailing zeros at DOUT and have no effect on converter operation. Minimum cycle time is accomplished by using DOUT's rising edge as the EOC signal. Clock out the data with 12.5 clock cycles at full speed. Pull CS high after readOUTPUT CODE 11...111 11...110 11...101
ing the conversion's LSB. After the specified minimum time (tCS), CS can be pulled low again to initiate the next conversion.
Output Coding and Transfer Function
The data output from the MAX1240/MAX1241 is binary, and Figure 10 depicts the nominal transfer function. Code transitions occur halfway between successiveinteger LSB values. If VREF = +2.500V, then 1 LSB = 610V or 2.500V/4096.
____________Applications Information
Connection to Standard Interfaces
The MAX1240/MAX1241 serial interface is fully compatible with SPI/QSPI and MICROWIRE standard serial interfaces (Figure 11). If a serial interface is available, set the CPU's serial interface in master mode so the CPU generates the serial clock. Choose a clock frequency up to 2.1MHz. 1) Use a general-purpose I/O line on the CPU to pull CS low. Keep SCLK low. 2) Wait the for the maximum conversion time specified before activating SCLK. Alternatively, look for a DOUT rising edge to determine the end of conversion. 3) Activate SCLK for a minimum of 13 clock cycles. The first falling clock edge produces the MSB of the DOUT conversion. DOUT output data transitions on SCLK's falling edge and is available in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Data can be clocked into the P on SCLK's rising edge. 4) Pull CS high at or after the 13th falling clock edge. If CS remains low, trailing zeros are clocked out after the LSB.
FULL-SCALE TRANSITION
FS = VREF - 1LSB 1LSB = VREF 4096 00...011 00...010 00...001 00...000 0 1 2 3 INPUT VOLTAGE (LSBs) FS FS - 3/2LSB
Figure 10. Unipolar Transfer Function, Full Scale (FS) = VREF 1LSB, Zero Scale (ZS) = GND
______________________________________________________________________________________
11
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO MAX1240/MAX1241
5) With CS = high, wait the minimum specified time, tCS, before initiating a new conversion by pulling CS low. If a conversion is aborted by pulling CS high before the conversion's end, wait for the minimum acquisition time, tACQ, before starting a new conversion. CS must be held low until all data bits are clocked out. Data can be output in two bytes or continuously, as shown in Figure 8. The bytes contain the result of the conversion padded with one leading 1, and trailing 0s.
a) SPI I/O SCK MISO +3V CS SCLK DOUT
MAX1240 MAX1241
SS
SPI and MICROWIRE
When using SPI or MICROWIRE, set CPOL = 0 and CPHA = 0. Conversion begins with a CS falling edge. DOUT goes low, indicating a conversion in progress. Wait until DOUT goes high or until the maximum specified 7.5s conversion time elapses. Two consecutive 1-byte reads are required to get the full 12 bits from the ADC. DOUT output data transitions on SCLK's falling edge and is clocked into the P on SCLK's rising edge. The first byte contains a leading 1, and seven bits of conversion result. The second byte contains the remaining five bits and three trailing zeros. See Figure 11 for connections and Figure 12 for timing.
CS SCK MISO +3V CS SCLK DOUT
SS b) QSPI
MAX1240 MAX1241
I/O SK SI
CS SCLK DOUT
QSPI
Set CPOL = CPHA = 0. Unlike SPI, which requires two 1-byte reads to acquire the 12 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the data. The MAX1240/MAX1241 requires 13 clock cycles from the P to clock out the 12 bits of data with no trailing zeros (Figure 13). The maximum clock frequency to ensure compatibility with QSPI is 2.097MHz.
MAX1240 MAX1241
c) MICROWIRE
Figure 11. Common Serial-Interface Connections to the MAX1241
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 14 shows the recommended system ground connections. Establish a single-point analog ground ("star" ground point) at GND, separate from the logic ground. Connect all other analog grounds and DGND to this star ground point for further noise reduction. No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply may affect
the ADC's high-speed comparator. Bypass this supply to the single-point analog ground with 0.1F and 4.7F bypass capacitors. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, a 10 resistor can be connected as a lowpass filter to attenuate supply noise (Figure 14).
12
______________________________________________________________________________________
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO MAX1240/MAX1241
1ST BYTE READ SCLK CS tCONV DOUT* D11 MSB EOC *WHEN CS IS HIGH, DOUT = HIGH -Z D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB HIGH-Z 2ND BYTE READ
Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
SCLK CS tCONV DOUT* D11 MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB HIGH-Z
EOC *WHEN CS IS HIGH, DOUT = HIGH -Z
Figure 13. QSPI Serial Interface Timing (CPOL = CPHA = 0)
SUPPLIES +3V +3V GND
R* = 10 4.7F
0.1F VDD GND +3V DGND
MAX1240 MAX1241
*OPTIONAL
DIGITAL CIRCUITRY
Figure 14. Power-Supply Grounding Condition
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13
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO MAX1240/MAX1241
__Ordering Information (continued)
PART MAX1240AEPA MAX1240BEPA MAX1240CEPA MAX1240AESA MAX1240BESA MAX1240CESA MAX1240AMJA MAX1240BMJA MAX1240CMJA MAX1241ACPA MAX1241BCPA MAX1241CCPA MAX1241ACSA MAX1241BCSA MAX1241CCSA MAX1241BC/D MAX1241AEPA MAX1241BEPA MAX1241CEPA MAX1241AESA MAX1241BESA MAX1241CESA MAX1241AMJA MAX1241BMJA MAX1241CMJA TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C PINPACKAGE 8 Plastic DIP 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO 8 SO 8 CERDIP** 8 CERDIP** 8 CERDIP** 8 Plastic DIP 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO 8 SO Dice* 8 Plastic DIP 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO 8 SO 8 CERDIP** 8 CERDIP** 8 CERDIP** INL (LSB) 1/2 1 1 1/2 1 1 1/2 1 1 1/2 1 1 1/2 1 1 1 1/2 1 1 1/2 1 1 1/2 1 1
* Dice are specified at TA = +25C, DC parameters only. ** Contact factory for availability and processing to MIL-STD-883.
___________________Chip Information
TRANSISTOR COUNT: 2558 SUBSTRATE CONNECTED TO GND
14
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+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO
________________________________________________________Package Information
PDIPN.EPS
MAX1240/MAX1241
______________________________________________________________________________________
SOICN.EPS
15
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO MAX1240/MAX1241
___________________________________________Package Information (continued)
CDIPS.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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